Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors

We present a new nonconventional approach for designing and organizing register rename mappers that can be applied in modern out-of-order processor chips. A content-addressable memory (CAM) configuration optimal for such a register mapper application was developed. The structure of the CAM and search engine, described in this paper, facilitates the implementation of the register mapper as a group of custom arrays. Each array is dedicated to executing a specific function. Among the functions we implemented are allocation of registers, maintaining the register map and status, source lookup, saving a shadow copy of the register map, and freeing up of registers. We made a novel implementation of the register mapper to provide rename resources for the IBM POWER4e chip, which provides the processing power for the IBM eServere p690. Such register renaming allows for a high level of concurrency in the pipeline and contributes to superior machine performance.